The metal-oxide semiconductor field-effect transistor (MOSFET or MOS device) is a dominant and important device in fabricating memory devices and integrated circuits, and various types of MOSFETS are known. MOSFET technology includes NMOS and CMOS technology, the former comprising n-channel MOS devices and the latter comprising n-channel and p-channel devices integrated on the same chip. Other acronyms are used to identify MOSFETs, including DMOS (wherein "D" stands for "diffusion" or "double diffusion"), PMOS (p-channel MOS), IGBT (Insulated Gate Bipolar Transistor), BiCMOS (CMOS having bipolar devices), and DGDMOS (Dual Gate DMOS).
MOS devices may be integrated together or with other components or devices to form memory cells. Static random access memory (SRAM) cells are commonly used as embedded memory because they are fast, dissipate low power, and easy to use. In comparison, dynamic random access memory (DRAM) and flash electrically-programmable read-only memory (EPROM) cells require overhead circuitry and additional processing costs as compared with SRAM cells. However, a disadvantage of SRAM cells is that traditionally they have required six transistors of which two are PMOS, whereas a DRAM cell needs only one transistor and one capacitor. A schematic circuit representation of a six-transistor SRAM is shown in FIG. 1, including two n-type drive transistors M.sub.1 and M.sub.2, where the gate of one transistor is connected to the gate of the other transistor with metal line 8.
Efforts thus have been addressed to reducing the cell size of SRAM's. For example, U.S. Pat. No. 5,438,538 to Hashimoto, "Static Random Access Memory for Gate Array Devices," assigned to Texas Instruments Inc. (incorporated herein), shows a SRAM cell comprising two n-channel pass gate transistors, two n-channel drive transistors, and two p-channel transistors, with a resistance element connecting the p-channel transistors to effectively reduce the size of these transistors below the size of the drive transistors. U.S. Pat. No. 5,867,443 to Linderman, "Shared Bitline Heterogeneous Memory," issued Feb. 2, 1999, shows a five-transistor SRAM cell accessed by a bitline merged with heterogeneous memories, such as EPROMs and DRAMS.
Vertical integration is also a viable approach for reducing cell size. An early solution involved using polysilicon resistors as the load and fabricating them on top of the NMOS transistors. The need to decrease the power and increase the stability to noise and soft errors inspired use of a full CMOS cell design. A useful design involved forming two PMOS load transistors in a polysilicon layer above four NMOS transistors in the substrate. See M. Ando, T. Okazawa, H. Furuta et al., "A 0.1 .mu.A Standby Current Bouncing Noise-Immune 1Mb SRAM," TECH. DIGEST SYMP VLSI CIRCUITS (1988), p. 49. As may be appreciated, those concerned with semiconductor technologies continue to search for new SRAM designs having smaller sizes and increased or comparable performance.